Inertial and Degradation Delay Model for CMOS Logic Gates

The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches

Asynchronous Modular Arbiter

A practical N-user arbiter and its implementation are presented in this correspondence. Because of the asynchronous character of its input variables (request signals), the design proposed is asynchronous and keeps in mind the possibility of metastable operations. The structure of the arbiter is very simple and modular

Low Power Implementation of Trivium Stream Cipher

This paper describes a low power hardware implementation of the Trivium stream cipher based on shift register parallelization techniques. The de-sign was simulated with Modelsim, and synthesized with Synopsys in three CMOS technologies with different gate lengths: 180nm, 130nm and 90 nm. The aim of this paper is to evaluate the suitability of this technique and compare the power consumption and the core area of the low power and standard implemen-tations. The results show that the application of the technique reduces power consumption by more than 20% with only a slight penalty in area and operating frequency.Junta de Andalucía P08-TIC-03674info:eu-repo/grantAgreement/EC/FP5/01867Ministerio de Ciencia e Innovación TEC2010-16870/MI

Fault Injection on FPGA implementations of Trivium Stream Cipher using Clock Attacks

Ministerio de Economía y Competitividad TEC2010-16870Ministerio de Economía y Competitividad TEC2013-45523-RMinisterio de Economía y Competitividad CSIC 201550E03

Fault Attack on FPGA implementations of Trivium Stream Cipher

This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and elements that analyze if a fault has been introduced, the number of faults introduced and its position in the inner state. The results obtained demonstrate the vulnerability of these implementations against fault attacks. As far as we know, this is the first time that experimental results of fault attack over Trivium are presented.Ministerio de Economía y Competitividad TEC2010-16870Ministerio de Economía y Competitividad TEC2013-45523- RMinisterio de Economía y Competitividad CSIC 201550E039

Selective Clock-Gating for Low Power/Low Noise Synchronous Counters

The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to reduce the power consumption as well as the switching noise generation. A measurement methodology to establish right comparisons between different implementations of gateclocked counters is presented. Basically two ways of applying clock gating are considered: clock gating on independent bits and clock gating on groups of bits. The right selection of bits where clock gating must be applied and the suited composition of groups of bits is essential when applying this technique. We have found groupment of bits is the best option when applying clock gating to reduce power consumption and specially to reduce noise generation.Ministerio de Ciencia y Tecnología TIC2000-1350Ministerio de Ciencia y Tecnología TIC2001- 228

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits

This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how the choice of a suited clocking scheme for the digital part reduces the switching noise, thus alleviating the problematic associated to limitations of performances in mixed-signal Analog/Digital Integrated Circuits. Simulation data of a pipelined XOR chain using both a single-phase and a two-phase clocking schemes, as well as of two nbit counters with different clocking styles lead, as conclusions, to recommend multiple clock-phase and asynchronous styles for reducing switching noise

Metodologia orientada a la elección de FPGAs con prioridad en el consumo de potencia

En este trabajo se presenta una metodología de diseño orientada a explorar el cada vez más amplio conjunto de FPGAs con el fin de seleccionar la mejor opción. Los parámetros que se utilizan para realizar la exploración son los recursos consumidos, la frecuencia de operación y el consumo de potencia. Sobre este último parámetro, el más difícil de medir, se hace un especial énfasis. Se exploran dos fabricantes (Altera y Xilinx), dos familias diferentes de cada fabricante y dos subfamilias dentro de cada familia, una de la gama alta y otra de la gama baja. Esta exploración se ha realizado implementando dos circuitos que realizan la operación división de números de 64 bits usando dos algoritmos con plena vigencia.España, Ministerio de Educación y Ciencia TEC2007-65105/MICEspaña, Junta de Andalucía TIC-360

Delay degradation effect in submicronic CMOS inverters

This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is demonstrated, providing a quantifying model. Fully characterization as a function of design variables and external conditions is carried out, making the model suitable for using in library characterization as well as simulation at a transistor level. Comparison with HSPICE level 6 simulations shows satisfactory accuracy for timing evaluation.Comisión Interministerial de Ciencia y Tecnología TIC 95-009

Montaje de un amplificador de audio en las prácticas de electrónica analógica

En esta comunicación se presenta el rediseño de las prácticas de laboratorio de la asignatura Electrónica Analógica con el objetivo de que el alumno monte un sistema de mediana complejidad. Estas prácticas son obligatorias y se realizan en sesiones de dos horas, por lo que el sistema ha de cumplir con las características de que sea modular y cubra gran parte de los contenidos de la asignatura. La asignatura Electrónica Analógica se imparte en el segundo curso de la titulación de Ingeniería Técnica Industrial, especialidad de Electrónica Industrial.Ministerio de Educación y Ciencia TEC2007-65105/MICJunta de Andalucía TIC-360